The present invention relates to a clock signal generating circuit for digital circuitry included in, e.g., a microcomputer and, more particularly, to a clock signal generating circuit for generating a rectangular clock signal whose duty cycle is 50%.
The problem with a conventional a clock signal generating circuit is that both a clock buffer section for a stabilization detecting section and an output buffer section included in the circuit output clock signals. Particularly, the clock buffer section continuously outputs a clock signal even after oscillation has been stabilized. The clock signal output from the clock buffer section is apt to turn out noise in a clock signal whose duty cycle is 50%.
Technologies relating to the present invention are disclosed in, e.g., Japanese Patent Laid-Open Publication No. 63-67822.